In high density DRAMS with PMOS array transistors, various circuit and device features create limitations in the magnitude of voltage swings achievable on the DRAM's wordlines. In FIG. 1, a prior art DRAM cell is shown with a wordline driver that employs both p and n channel transistors. Each DRAM cell includes a PMOS transistor 10 and capacitor 12 which, in combination, store a charge indicative of a stored bit. The cell is interrogated by application of appropriate potentials to wordline 14 and bitline 16. The output from a cell is differentially detected in a sense amplifier 18, in response to the application of an output on bitline 16 and its complement on bitline 20.
Wordline 14 is powered from a wordline driver 21 which comprises a PMOS transistor 22 whose source is connected to a supply Vdd, and an NMOS transistor 24 whose drain is connected to ground.
Assume that the memory cell has already been written into and that capacitor 12 contains a charge indicative of a bit value. Wordline 14 and bitline 16 are then simultaneously driven towards ground to enable PMOS transistor 10 to conduct and to reflect onto bitline 16, the charge state on capacitor 12. This is accomplished by applying a decoder input to terminal 26 which, in turn, causes NMOS transistor 24 to become conductive and PMOS transistor 22 non-conductive. A like voltage transition occurs on bitline 16, via the operation of sense amplifier 18.
Given the above conditions, if a charge exists on capacitor 12, PMOS transistor 10 is rendered conductive and an output is produced on bitline 16 which is detected by sense amplifier 18. However, when both wordline 14 and bitline 16 are at ground level, node 28 between PMOS transistor 10 and capacitor 12 only falls to the magnitude of the threshold potential Vt of PMOS transistor 10. Thus, the voltage at node 28 traverses between Vdd and .vertline.Vt.vertline. (rather than ground). The application of a more negative potential to the drain of NMOS transistor 24 will not solve the problem, since NMOS transistor 24 is constructed on a grounded P substrate. Such a negative potential applied to the drain will cause a forward bias to be applied to the substrate junction and render the transistor inoperative.
Since the objective is to pull wordline 14 to a more negative potential, while simultaneously using a grounded P substrate, the prior art has suggested the use of a PMOS transistor as the "pull-down" transistor. Such a prior art circuit is shown in FIG. 2, wherein PMOS transistor 30 has been substituted for NMOS transistor 24 shown in FIG. 1.
In FIG. 3, the semiconductor structure of PMOS transistor 30 is shown in cross section. An N-well 32 isolates the various contact regions, provides for a conduction channel, and isolates PMOS transistor 30 from substrate 34. N-well 32 is biased by the application of Vdd to contact 36. In this instance, in lieu of ground being applied to the drain of PMOS transistor 30, a more negative supply voltage (-V) is connected thereto.
When wordline 14 is to be pulled down, a voltage Vc is applied to control terminal 40 and its complement to terminal 42 (FIG. 2). If it is assumed that Vc is at ground level, the potential on wordline 14 falls to the higher voltage of Vc+.vertline.VT.vertline. or -V. If Vc+.vertline.Vt.vertline. falls below -V, the wordline is clamped to -V by the potential on the drain of PMOS transistor 30. Since N-well 32 is biased at Vdd, the application of Vc (e.g. ground) to terminal 40 applies a potential across N-well 32 and, as a result, causes an increase in the body effect of transistor 30 and a concomitant increase in its threshold voltage Vt. Thus, an even more negative Vc is now needed to enable formation of a conduction channel beneath the gate of transistor 30. Therefore, while the application of -V to the drain of transistor 30 aids in the pull-down of wordline 14, the negative control potential Vc creates a counter-vailing affect within transistor 30 which must be accommodated by a further adjustment of Vc. As the N-well, which isolates transistor 30 from substrate 34, also encompasses a plurality of other PMOS transistors, it is undesirable to place such a high reverse bias across the N-well.
Other prior art showing various wordline decoding and level setting techniques can be found in the following prior art.
In U.S. Pat. No. 4,514,829, a CMOS decoder and driver circuit for a DRAM memory are shown wherein the pitch of the decoder is twice that of the wordlines and the number of decoders is thereby reduced by one half.
In U.S. Pat. No. 4,618,784 to Chappell et al., a decoder circuit employing an n-channel pull-down transistor is shown.
In U.S. Pat. No. 4,639,622 to Goodwin et al., a wordline boost circuit is described wherein an additional pair of MOS transistors are connected to a clock signal and produce a voltage boosting signal. A capacitor connects the boost circuit to an output lead and applies a boost signal to enhance voltage level changes on the output lead. In U.S. Pat. No. 4,678,941 to Chao et al., a decoder circuit having a boost word-line clock is described. The system described by Chao et al. employs a negative substrate bias which thus avoids junction forward-biasing which can result from voltage undershoots below ground.
In U.S. Pat. No. 4,704,706 to Nakano et al., a wordline booster circuit employs a precharged capacitor in a boot strap circuit configuration. The Nakano et al. circuit employs only NMOS transistors and thus, does not have the same threshold potential problems exhibited in a PMOS arrangement.
In U.S. Pat. No. 4,843,261 to Chappell et al., still another CMOS decoder/driver circuit is described using an n channel transistor for pull down purposes.
In IBM Technical Disclosure Bulletin, Vol. 28, No. 6, November 1985, pp. 2660-2662, another wordline boost circuit is shown wherein charged capacitances are employed to pull a wordline to a more negative potential than ground. Complementary MOS transistors are used in the aforementioned circuit.
It is an object of this invention to provide an improved PMOS wordline boost circuit for a DRAM.
It is another object of this invention to provide a PMOS wordline boost circuit which avoids increased body effects within the PMOS driver transistors.
It is still another object of this invention to provide a PMOS wordline boost circuit which provides an improved wordline voltage transition, without the need for additional, exterior-generated logic potentials.